Tuesday, 10 July 2012

On the subject of the Overflow flag

The reference is somewhat unhelpful with this. It says it 'monitors' the output signal from the adder, and clocks the JK Flip Flop that is the overflow bit on T7 (e.g. last bit shifted) when there is an arithmetic instruction (DCA, ADD, SUB).

It is 'initially reset' apparently which could mean either (i) it resets on reset or (ii) it resets in the fetch/execute cycle. Either is feasible as a sensible design, though (ii) is better because otherwise you can't clear the carry.

On the circuit the J line is set to the Adder Carry Out, the Reset to 'Clr' and the K line to OVFC. The FlipFlop is clocked by the system clock.  The circuit would suggest that the overflow flip flop is cleared by the system reset button.

J is the Carry out from the adder. The adder appears to operate whether you are adding or not. However, the ASD line forces the carry in to be zero outside ASD commands, and the input is gated off, so there cannot be a carry out on the 7th bit (because Carry In is zero and one of the inputs is zero).

However, this line must oscillate between 0 and 1 as the carry comes from the adder, otherwise the adder circuit doesn't work. So when CLK occurs the inputs to J must be 0 or 1, and K is OVFC.  The problem is I can't see where OVFC comes from - it calls it the "Overflow Control". It doesn't appear to be on any of the schematics.

The reference however states that during T7 J and K are both '1' if there is a carry out and this causes the overflow flag to change.  This would suggest OVFC = ASD.T7 e.g. set on the final calculation for an ASD instruction.

The thing that puzzles me is if J is toggling between 1 and 0 on carry out from sub bits in the serial addition and K is 0 then the JK Flip Flop will set itself to '1' when J=1 K=0 and CLK occurs.  If J=K=1 and CLK occurs then this does toggle the flip flop to its opposite state.

So if this is right, the the overflow is cleared at reset and set whenever there is a carry out from any bit position in the adder, and toggled when the 7th bit is non-zero.

This doesn't sound correct. You want it clocked on T7.ASD really, so that the value is stored on the 7th cycle of an add/subtract/decrement instruction.

I'm wondering if the given circuit diagram is actually correct.

This all sounds deeply silly. Mind you you could argue the same about the RetroChallenge :)

And as you can't access the overflow (without wiring in the SKC line) it makes absolutely no difference :)

Unless I have a magic moment, I'm going to assume it is cleared on reset and set on T7.ASD.CarryOut

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