The NRI 832 is quite limited. This isn't actually anything to do with the core design. It is mostly to do with the shortage of program space, which is related to the cost of TTL memory - this is why the original design can operate with no memory at all, something of a record low for a home computer.
I want to upgrade the design, while retaining backward compatibility. However, in the spirit of RetroChallenge, this must be something that is feasible - sensibly - with TTL Logic Chips and without too much complexity.
There is a currently 5 bit program counter. The plan is to add a 4 bit page register to the design, giving a whopping 512 bytes of program memory.
This would involve having a presettable 4 bit counter which can be written to using an used instruction. The obvious choice is STA for values from 0-F which currently does absolutely nothing as you cannot write to the 'ROM' space. This is better than the alternative (appropriating OPR instructions) because it does not require any changes to the OPR decoding.
So the output from the STA/EXEC/E2 line - which triggers the physical write, would be ANDed with the Not(A4) line to produce a signal which would latch the counter with the lower 4 bits of the instruction register.
The clock pin would be connected to bit 4 of the program counter, so when a carry out from that line occurred it would clock the page register, so that [Page1] [0x1F] would go to [Page2] [0x00] when incremented.
Additionally, this latching signal could reset the Program Counter, thus effectively making STA n 0-F a long jump to address n * 32
Memory reads for program and data would operate using this paged register, so each little 32 byte block would operate independently. This would be program code/constant data ; there would be no write access to this extended memory.
The exception to this would be memory access from 10-1F. The locations that access this memory would ignore the page register and read and write from the TTL as usual - allowing read/write access to 16 bytes of data memory.
This would mean that constants would tend to be placed in the first 16 bytes of a 32 byte page, because they could not otherwise be accessed (because loading and storing would be directed to page zero for addresses 10-1F.
This has the advantage of making it compatible with the standard 16 byte version of the NRI 832, which would ignore the page instructions.
Or I could just do the obvious and use a 6502. But that wouldn't be as much fun ......